Check out the animations under "Clock Distributions" (numbers 19 to 25. It shows how the propagation of the clock across the die is affected by frequency (When a part of the fabric/tree is up or down it represents 1 and 0 respectively).
My favorite is the SymTree and Non-Uniform SymTree (23 and 24) which shows how having a non uniform load at various parts of the chip and a fixed tree structure affects how long each part of the chip is at a 1 or 0 state (i.e. a low load part of the chip will spend more time at a stabilized 1 or 0, while a heavy capacitive load at one part can not even reach a true 1 or 0).
Check out the animations under "Clock Distributions" (numbers 19 to 25. It shows how the propagation of the clock across the die is affected by frequency (When a part of the fabric/tree is up or down it represents 1 and 0 respectively).
My favorite is the SymTree and Non-Uniform SymTree (23 and 24) which shows how having a non uniform load at various parts of the chip and a fixed tree structure affects how long each part of the chip is at a 1 or 0 state (i.e. a low load part of the chip will spend more time at a stabilized 1 or 0, while a heavy capacitive load at one part can not even reach a true 1 or 0).