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I had some fun with MyHDL several months ago, which lets you compile Python code (using MyHDL) into Verilog (or VHDL). http://www.myhdl.org/doku.php (Some flip flop examples: http://www.myhdl.org/doku.php/cookbook:ff )

There's nothing inherently special about Verilog/VHDL as concurrent languages--I imagine a very slick-looking Clojure module could be built as well. MyHDL let me reason about the program much more easily than a Verilog equivalent, all around the block in the cases of synchronous execution, blocking/non-blocking statements and integers ( http://www.myhdl.org/doku.php/why ). Also, (mostly) painless simulation and tests!

Though I would tend to agree that a C to Verilog system would be a step back; MyHDL makes heavy use of decorators and generators and other goodies that come from the functional programming world. C doesn't really work well there; you can hack it in but at that point you might as well just use Verilog.



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